COMPUTER SYSTEM ARCHITECTURE MCQS PART 10

COMPUTER SYSTEM ARCHITECTURE MCQS PART 10

1. A ___________development system and an ______are essential tools for writing large assembly language programs.
Ans: Microprocessor, assembler

2. In an operation performed by the ALU, carry bit is set to 1 if the end carry C 8 is________. It is cleared to 0 (zero) if the carry is ______
Ans: One, zero

3. A successive A/D converter is
(A) a high-speed converter.
(B) a low speed converter.
(C) a medium speed converter.
(D) none of these.
Ans: C

4. When necessary, the results are transferred from the CPU to main memory by
(A) I/O devices.
(B) CPU.
(C) shift registers.
(D) none of these.
Ans: C

5. A combinational logic circuit which sends data coming from a single source to two or more separate destinations is
(A) Decoder.
(B) Encoder.
(C) Multiplexer.
(D) Demultiplexer.
Ans: D

6. In which addressing mode the operand is given explicitly in the instruction
(A) Absolute.        
(B) Immediate.          
(C) Indirect.          
(D) Direct.
Ans: B
7. A stack organized computer has
(A) Three-address Instruction.
(B) Two-address Instruction.
(C) One-address Instruction.
(D) Zero-address Instruction.
Ans: D

8. A Program Counter contains a number 825 and address part of the instruction contains the number 24. The effective address in the relative address mode, when an instruction is read from the memory is
(A) 849.
(B) 850.
(C) 801.
(D) 802.
Ans: B

9. A page fault
(A) Occurs when there is an error in a specific page.   
(B) Occurs when a program accesses a page of main memory.
(C) Occurs when a program accesses a page not currently in main memory.
(D) Occurs when a program accesses a page belonging to another program.
Ans: C

10. The load instruction is mostly used to designate a transfer from memory to a processor register known as____.
A. Accumulator
B. Instruction Register
C. Program counter
D. Memory address Register
Ans: A