Magme Guru: Digital Electronics

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Tuesday, April 28, 2020

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 09

1. The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions.
(A)By applying J = 0, K = 0 and using a clock.
(B)By applying J = 1, K = 0 and using the clock.
(C)By applying J = 1, K = 1 and using the clock.
(D)By applying a synchronous preset input.
Ans: C Explanation: Preset state of JK Flip-Flop =1
With J=1 K=1 and the clock next state will be complement of the present state.

2. The information in ROM is stored
(A) By the user any number of times.
(B) By the manufacturer during fabrication of the device.
(C) By the user using ultraviolet light.
(D)By the user once and only once.
Ans: B

3. The conversation speed of an analog to digital converter is maximum with the following technique.
(A) Dual slope AD converter.
(B) Serial comparator AD converter.
(C) Successive approximation AD converter.
(D)Parallel comparator AD converter.
Ans: D

4.A weighted resistor digital to analog converter using N bits requires a total of
(A)N precision resistors.
(B) 2N precision resistors.
(C) N + 1 precision resistors.
(D) N – 1 precision resistors.
Ans: A

5. The 2’s complement of the number 1101110 is
(A) 0010001.
(B) 0010001.
(C) 0010010.
(D) None.
Ans: C Explanation: 1’s complement of 1101110 is = 0010001
Thus 2’s complement of 1101110 is = 0010001 + 1 = 0010010

6. The decimal equivalent of Binary number 10101 is
(A) 21
(B) 31
(C) 26
(D) 28
Ans: A Explanation: 1x2^4 + 0x2^3 +1x2^2 +0x2^1 + 1x2^0 = 16 + 0 + 4 + 0 + 1 = 21.

7. How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB
(A) 1, 1
(B) 4, 2
(C) 3, 2
(D) 2, 3
Ans: A Explanation: There are three product terms, so three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

8. How many select lines will a 32:1 multiplexer will have
(A) 5.
(B) 8.
(C) 9.
(D) 11.
Ans: A Explanation: For 32 inputs, 5 select lines will be required, as 25 = 32.

Magme Guru 0

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 08

1.How many two-input AND and OR gates are required to realize Y=CD+EF+G
(A) 2,2.
(B) 2,3.
(C) 3,3.
(D) none of these.
Ans: A
Explanation: Y=CD+EF+G
Number of two input AND gates=2
Number of two input OR gates = 2
One OR gate to OR CD and EF and next to OR of G & output of first OR gate.

2. Which of following can not be accessed randomly
(A)DRAM.
(B) SRAM.
(C) ROM.
(D) Magnetic tape.
Ans: D Explanation: Magnetic tape can only be accessed sequentially.

3. The excess-3 code of decimal 7 is represented by
(A) 1100.
(B) 1001.
(C) 1011.
(D) 1010.
Ans: D
Explanation: An excess 3 code is always equal to the binary code +3

4. When an input signal A=11001 is applied to a NOT gate serially, its output signal is
(A) 00111.
(B) 00110.
(C) 10101.
(D) 11001.
Ans: B
Explanation: As A=11001 is serially applied to a NOT gate, first input applied will be LSB 00110.

5. The result of adding hexadecimal number A6 to 3A is
(A)DD.
(B) E0.
(C) F0.
(D) EF.
Ans: B

6. A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate?
(A)OR
(B) AND
(C) XOR
(D) NAND
Ans: D
Explanation: NAND can generate any logic function.

7. The logic 0 level of a CMOS logic device is approximately
(A)1.2 volts
(B) 0.4 volts
(C) 5 volts
(D) 0 volts
Ans: D
Explanation: CMOS logic low level is 0 volts approx.

8. Karnaugh map is used for the purpose of
(A)Reducing the electronic circuits used.
(B) To map the given Boolean logic function.
(C)To minimize the terms in a Boolean expression.
(D)To maximize the terms of a given a Boolean expression.
Ans: C

9. A full adder logic circuit will have
(A)Two inputs and one output.
(B)Three inputs and three outputs.
(C) Two inputs and two outputs.
(D) Three inputs and two outputs.
Ans: D Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.

10. An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately
(A)1 MHz.
(B) 500 MHz
(C) 2 MHz.
(D) 4 MHz.
Ans: A
Explanation: Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.

Magme Guru 0

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 07

1. How many flip-flops are required to construct mod 30 counter
(A) 5
(B) 6
(C) 4
(D) 8
Ans: A
Explanation: Mod - 30 counter +/- needs 5 Flip-Flop as 30 < 25 Mod - N counter counts total ' N ' number of states.
To count 'N' distinguished states we need minimum n FlipFlop's as [N = 2n] For eg. Mod 8 counter requires 3 Flip-Flop's (8 = 23)

2. How many address bits are required to represent a 32 K memory
(A)10 bits.
(B) 12 bits.
(C) 14 bits.
(D) 16 bits.
Ans: D
Explanation: 32K = 25 x 210 = 215,
Thus 15 address bits are required, Only 16 bits can address it.

3. The number of control lines for 16 to 1 multiplexer is
(A) 2.
(B) 4.
(C) 3.
(D) 5.
Ans: B Explanation: As 16 = 24, 4 Select lines are required.

4. Which of following requires refreshing?
(A)SRAM.
(B) DRAM.
(C) ROM.
(D) EPROM.
Ans: B

5. Shifting a register content to left by one bit position is equivalent to
(A)division by two.
(B) addition by two.
(C) multiplication by two.
(D) subtraction by two.
Ans:C

6. The decimal equivalent of (1100)2 is
(A) 12
(B) 16
(C) 18
(D) 20
Ans: A
Explanation: (1100)2 = (12)10

7. The binary equivalent of (FA)16 is
(A) 1010 1111
(B) 1111 1010
(C) 10110011
(D) none of these
Ans: B
Explanation: (FA)16 = (11111010)10

8.The output of SR flip flop when S=1, R=0 is
(A) 1
(B) 0
(C) No change
(D) High impedance
Ans: A
Explanation: As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.

9. The number of flip flops contained in IC 7490 is
(A) 2.
(B) 3.
(C) 4.
(D) 10.
Ans: A

10. The number of control lines for 32 to 1 multiplexer is
(A) 4.
(B) 5
(C) 16.
(D) 6.
Ans: B
Explanation: The number of control lines for 32 (25) and to select one input among them total 5 select lines are required.

Magme Guru 0

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 06

1. Using complement method negative numbers can also be subtracted.
In a positive logic system, logic state 1 corresponds to
(A)positive voltage
(B) higher voltage level
(C) zero voltage level
(D) lower voltage level
Ans: B

2. We decide two voltages levels for positive digital logic. Higher voltage represents logic 1 & a lower voltage represents logic 0. The commercially available 8-input multiplexer integrated circuit in the TTL family is
(A) 7495.
(B) 74153.
(C) 74154.
(D) 74151.
Ans: B
Explanation: MUX integrated circuit in TTL is 74153.

3. CMOS circuits are extensively used for ON-chip computers mainly because of their extremely
(A)low power dissipation.
(B) high noise immunity.
(C) large packing density.
(D) low cost.
Ans: C
Explanation: Because CMOS circuits have large packing density.

4.The MSI chip 7474 is
(A) Dual edge triggered JK flip-flop (TTL).
(B)Dual edge triggered D flip-flop (CMOS).
(C)Dual edge triggered D flip-flop (TTL).
(D) Dual edge triggered JK flip-flop (CMOS).
Ans: C
Explanation: MSI chip 7474 dual edge triggered D Flip-Flop.

5. Which of the following memories stores the most number of bits
(A)a 5M× 8 memory.
(B) a 1M × 16 memory.
(C) a 5M × 4 memory.
(D) a 1M ×12 memory.
Ans: A
Explanation: 5Mx8 = 5 x 220 x 8 = 40M (max)

6. The process of entering data into a ROM is called
(A)burning in the ROM
(B) programming the ROM
(C) changing the ROM
(D) charging the ROM
Ans: B
Explanation: The process of entering data into ROM is known as programming the ROM.

7. When the set of input data to an even parity generator is 0111, the output will be
(A) 1
(B) 0
(C) Unpredictable
(D) Depends on the previous input
Ans: B
Explanation: In even parity generator if number of 1 is odd then output will be zero.

8. The number 140 in octal is equivalent to
(A) (96)10
(B) (86)10
(C) (90)10
(D) none of these
Ans: A
Explanation: (140)8 = (96)10
1 x 8^2 + 4 x 8 + 0x 1 = 64 + 32 = 96

9. The NOR gate output will be low if the two inputs are
(A) 00
(B) 01
(C) 10
(D) 11
(E) B,C,and D
Ans: E
Explanation: O/P is low if any of the I/P is high

10.Which of the following is the fastest logic?
(A)ECL
(B) TTL
(C) CMOS
(D) LSI
Ans: A

Magme Guru 0

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 05

1.How many select lines will a 16 to 1 multiplexer will have
(A) 4
(B) 3
(C) 5
(D) 1
Ans: A Explanation: In 16 to 1 MUX four select lines will be required to select 16 ( 24 ) inputs.

2. How many address bits are required to represent 4K memory
(A) 5 bits.
(B) 12 bits.
(C) 8 bits.
(D) 10 bits.
Ans: B Explanation: For representing 4K memory, 12 address bits are required as
    4K = 22 x 210 = 212     (1K = 1024 = 210)

3. For JK flipflop J = 0, K=1, the output after clock pulse will be
(A) 1.
(B) no change.
(C) 0.
(D) high impedance.
Ans: C
Explanation: J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So whatever be the previous output, the next state will be 0.

4. Which of following are known as universal gates
(A)NAND & NOR.
(B) AND & OR.
(C) XOR & OR.
(D) None.
Ans: A
Explanation: NAND & NOR are known as universal gates, because any digital circuit can be realized completely by using either of these two gates.

5. Which of the following memories stores the most number of bits
(A)64K × 8 memory.
(B) 1M × 8 memory.
(C) 32M × 8 memory.
(D) 64 × 6 memory.
Ans: C
Explanation: 32M x 8 stores most number of bits
25 x 220   = 225     (1M = 220 = 1K x 1K = 210 x 210)

6. How many flip flops are required to construct a decade counter
(A) 10
(B) 3
(C) 4
(D) 2
Ans: C Explanation: Decade counter counts 10 states from 0 to 9 ( i.e. from 0000 to 1001 ) Thus four FlipFlop's are required.

7. Which TTL logic gate is used for wired ANDing
(A)Open collector output
(B) Totem Pole
(C) Tri state output
(D) ECL gates
Ans: A
Explanation: Open collector output.

8. CMOS circuits consume power
(A) Equal to TTL
(B) Less than TTL
(C) Twice of TTL
(D) Thrice of TTL
Ans: B
Explanation: As in CMOS one device is ON & one is Always OFF so power consumption is low.

9. In a RAM, information can be stored
(A) By the user, number of times.
(B) By the user, only once.
(C) By the manufacturer, a number of times.
(D) By the manufacturer only once.
Ans: A
Explanation: RAM is used by the user, number of times.

10. The chief reason why digital computers use complemented subtraction is that it
(A)Simplifies the circuitry.
(B) Is a very simple process.
(C) Can handle negative numbers easily.
(D)Avoids direct subtraction.
Ans: C

Magme Guru 0

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 04

1. When signed numbers are used in binary arithmetic, then which one of the following notations would have unique representation for zero.
(A)Sign-magnitude.
(B) 1’s complement.
(C) 2’s complement.
(D) 9’s complement.
Ans: A

2. Which of following consume minimum power
(A)TTL.
(B) CMOS.
(C) DTL.
(D) RTL.
Ans: B
Explanation: CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS transistors are connected in complimentary mode, such that one device is ON & one is OFF.

3. In digital ICs, Schottky transistors are preferred over normal transistors because of their
(A)Lower Propagation delay.
(B) Higher Propagation delay.
(C) Lower Power dissipation.
(D) Higher Power dissipation.
Ans: A
Explanation: Lower propagation delay as shottky transistors reduce the storage time delay by preventing the transistor from going deep into saturation.

4. The following switching functions are to be implemented using a Decoder:
f1 =)m(1, 2, 4, 8,10,14) f2 =) m(2, 5, 9,11) f3 =) m(2, 4, 5, 6, 7)
The minimum configuration of the decoder should be
(A) 2 – to – 4 line.
(B) 3 – to – 8 line.
(C) 4 – to – 16 line.
(D) 5 – to – 32 line.
Ans: C
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

5. A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The maximum possible time required for change of state will be
(A) 15 ns.
(B) 30 ns.
(C) 45 ns.
(D) 60 ns.
Ans: A
Explanation: 15 ns because in synchronous counter all the flip-flops change state at the same time.

6. Words having 8-bits are to be stored into computer memory. The number of lines required for writing into memory are
(A) 1.
(B) 2.
(C) 4.
(D) 8.
Ans: D
Explanation: Because 8-bit words required 8 bit data lines.

7.The decimal equivalent of Binary number 11010 is
(A) 26.
(B) 36.
(C) 16.
(D) 23.
Ans: A Explanation: 11010 = 1 X 24 + 1 X 2 3 + 0 X 22 + 1 X 21 = 26

8. 1’s complement representation of decimal number of -17 by using 8 bit representation is
(A) 1110 1110
(B) 1101 1101
(C) 1100 1100
(D) 0001 0001
Ans: A
Explanation: (17)10 = (10001)2
In 8 bit = 00010001
1's Complement = 11101110

9.The excess 3 code of decimal number 26 is
(A) 0100 1001
(B) 01011001
(C) 1000 1001
(D) 01001101
Ans: B
Explanation: (26)10 in BCD is ( 00100110 ) BCD
Add 011 to each BCD 01011001 for excess – 3

10.How many AND gates are required to realize Y = CD+EF+G
(A) 4
(B) 5
(C) 3
(D) 2
Ans: D
Explanation: To realize Y = CD + EF + G
Two AND gates are required (for CD & EF).

Magme Guru 0

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 03

1. Which of the following is the fastest logic
(A)TTL
(B) ECL
(C) CMOS
(D) LSI
Ans: B
ECL is the fastest logic family of all logic families.
(High speeds are possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated.

2.If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is
(A) 1000 Hz
(B) 500 Hz
(C) 333 Hz
(D) 12.5 Hz.
Ans: D

3. Which of the memory is volatile memory
(A)ROM
(B) RAM
(C) PROM
(D) EEPROM
Ans: B
Explanation: RAM is a volatile memory (Volatile memory means the contents of the RAM get erased as soon as the power goes off.)

4. -8 is equal to signed binary number
(A) 10001000
(B) 00001000
(C) 10000000
(D) 11000000
Ans: A
Explanation: 8 is equal to signed binary number 10001000

5. DeMorgan’s first theorem shows the equivalence of
(A)OR gate and Exclusive OR gate.
(B)NOR gate and Bubbled AND gate.
(C)NOR gate and NAND gate.
(D)NAND gate and NOT gate
Ans: B

6. The digital logic family which has the lowest propagation delay time is
(A)ECL
(B) TTL
(C) CMOS
(D) PMOS
Ans: A
Explanation: The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).

7. The device which changes from serial data to parallel data is
(A)COUNTER
(B) MULTIPLEXER
(C) DEMULTIPLEXER
(D) FLIP-FLOP
Ans: C
Explanation: The device which changes from serial data to parallel data is demultiplexer. (A demultiplexer takes in data from one line and directs it to any of its N outputs depending on the status of the select inputs.)

8. A device which converts BCD to Seven Segment is called
(A)Encoder
(B) Decoder
(C) Multiplexer
(D) Demultiplexer
Ans: B
Explanation: device which converts BCD to Seven Segment is called DECODER. (A decoder coverts binary words into alphanumeric characters.)

9.The access time of ROM using bipolar transistors is about
(A)1 sec
(B) 1 msec
(C) 1 µsec
(D) 1 nsec.
Ans: C
Explanation: The access time of ROM using bipolar transistors is about 1 µ sec.

10. The A/D converter whose conversion time is independent of the number of bits is
(A)Dual slope
(B) Counter type
(C) Parallel conversion
(D) Successive approximation.
Ans: C
Explanation: The A/D converter whose conversion time is independent of the Number of bits is Parallel conversion.
(This type uses an array of comparators connected in parallel and comparators compare the input voltage at a particular ratio of the reference voltage).

Magme Guru 0

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 02

1.The Gray code for decimal number 6 is equivalent to
(A) 1100
(B) 1001
(C) 0101
(D) 0110
Ans: C

2. The digital logic family which has minimum power dissipation is
(A) TTL
(B) RTL
(C) DTL
(D) CMOS
Ans: D
Explanation: The digital logic family which has minimum power dissipation is CMOS.
(CMOS being an unipolar logic family, occupy a very small fraction of silicon Chip area)

3. The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either
(A) a NAND or an EX-OR
(B) an OR or an EX-NOR
(C) an AND or an EX-OR
(D) a NOR or an EX-NOR
Ans: D

4. Data can be changed from special code to temporal code by using
(A) Shift registers
(B) counters
(C) Combinational circuits
(D) A/D converters.
Ans: A
Explanation: Data can be changed from special code to temporal code by using Shift Registers. (A Register in which data gets shifted towards left or right when clock pulses are applied is known as a Shift Register.

5. A ring counter consisting of five Flip-Flops will have
(A)5 states
(B) 10 states
(C) 32 states
(D) Infinite states.
Ans: A
Explanation: A ring counter consisting of Five Flip-Flops will have 5 states.

6. The 2’s complement of the number 1101101 is
(A) 0101110
(B) 0111110
(C) 0110010
(D) 0010011
Ans: D
Explanation: The 2’s complement of the number 1101101 is 0010011
(1’s complement of the number 1101101 is 0010010
2’s complement of the number 1101101is 0010010 + 1 =0010011)

7. The correction to be applied in decimal adder to the generated sum is
(A) 00101
(B) 00110
(C) 01101
(D) 01010
Ans: B
Explanation: The correction to be applied in decimal adder to the generated sum is 00110.
When the four bit sum is more than 9 then the sum is invalid. In such cases, add +6(i.e. 0110) to the four bit sum to skip the six invalid states. If a carry is generated when adding 6, add the carry to the next four bit group .

8. When simplified with Boolean Algebra (x + y)(x + z) simplifies to
(A)x
(B) x + x(y + z)
(C) x(1 + yz)
(D) x + yz
Ans: D

9.The excess 3 code of decimal number 26 is
(A) 0100 1001
(B) 01011001
(C) 1000 1001
(D) 01001101
Ans: B
(26)10 in BCD is ( 00100110 ) BCD
Add 011 to each BCD 01011001 for excess – 3

10. The code where all successive numbers differ from their preceding number by single bit is
(A)Binary code.
(B) BCD.
(C) Excess – 3.
(D) Gray.
Ans: D
The code where all successive numbers differ from their preceding number by single bit is Gray Code.
(It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next.)

Magme Guru 0

TEACHING April 28, 2020

DIGITAL ELECTRONICS MCQS PART 01

1. The NAND gate output will be low if the two inputs are
(A) 00
(B) 01
(C) 10
(D) 11
Ans: D

2.What is the binary equivalent of the decimal number 368
(A) 101110000
(B) 110110000
(C) 111010000
(D) 111100000
Ans: A

3. The decimal equivalent of hex number 1A53 is
(A)6793
(B) 6739
(C) 6973
(D) 6379
Ans: B

4. (734)8 = ( )16
(A) C 1 D
(B) D C 1
(C) 1 C D
(D) 1 D C
Ans: D

5. The simplification of the Boolean expression (ABC)+ (ABC) is
(A) 0
(B) 1
(C) A
(D) BC
Ans: B

6. The number of control lines for a 8 – to – 1 multiplexer is
(A) 2
(B) 3
(C) 4
(D) 5
Ans: B
7. How many Flip-Flops are required for mod–16 counter?
(A) 5
(B) 6
(C) 3
(D) 4
Ans: D

8. EPROM contents can be erased by exposing it to
A. Ultraviolet rays.
B.Infrared rays.
C. Burst of microwaves.
D.Intense heat radiations
Ans: A

10. The hexadecimal number ‘A0’ has the decimal value equivalent to
(A) 80
(B) 256
(C) 100
(D) 160
Ans: D

Magme Guru 0

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Tuesday, April 28, 2020

DIGITAL ELECTRONICS MCQS PART 09

DIGITAL ELECTRONICS MCQS PART 09

DIGITAL ELECTRONICS MCQS PART 08

DIGITAL ELECTRONICS MCQS PART 08

DIGITAL ELECTRONICS MCQS PART 07

DIGITAL ELECTRONICS MCQS PART 07

DIGITAL ELECTRONICS MCQS PART 06

DIGITAL ELECTRONICS MCQS PART 06

DIGITAL ELECTRONICS MCQS PART 05

DIGITAL ELECTRONICS MCQS PART 05

DIGITAL ELECTRONICS MCQS PART 04

DIGITAL ELECTRONICS MCQS PART 04

DIGITAL ELECTRONICS MCQS PART 03

DIGITAL ELECTRONICS MCQS PART 03

DIGITAL ELECTRONICS MCQS PART 02

DIGITAL ELECTRONICS MCQS PART 02

DIGITAL ELECTRONICS MCQS PART 01

DIGITAL ELECTRONICS MCQS PART 01

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