DIGITAL ELECTRONICS MCQS PART 08

DIGITAL ELECTRONICS MCQS PART 08

1.How many two-input AND and OR gates are required to realize Y=CD+EF+G
(A) 2,2.    
(B) 2,3.        
(C) 3,3.    
(D)  none of these.
Ans: A
Explanation: Y=CD+EF+G
Number of two input AND gates=2
Number of two input OR gates = 2
One OR gate to OR CD and EF and next to OR of G & output of first OR gate.

2. Which of following can not be accessed randomly
(A)DRAM.      
(B) SRAM.      
(C) ROM.    
(D)  Magnetic tape.
Ans: D Explanation: Magnetic tape can only be accessed sequentially.

3. The excess-3 code of decimal 7 is represented by
(A) 1100.    
(B) 1001.     
(C) 1011.      
(D) 1010.
Ans: D
Explanation: An excess 3 code is always equal to the binary code +3

4. When an input signal A=11001 is applied to a NOT gate serially, its output signal is
(A) 00111.    
(B) 00110.   
(C) 10101.    
(D) 11001.
Ans: B
Explanation: As A=11001 is serially applied to a NOT gate, first input applied will be LSB 00110.

5. The result of adding hexadecimal number A6 to 3A is
(A)DD.    
(B) E0.    
(C) F0.    
(D) EF.
Ans: B

6. A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate?
(A)OR    
(B) AND    
(C) XOR    
(D) NAND
Ans: D
Explanation: NAND can generate any logic function.

7. The logic 0 level of a CMOS logic device is approximately
(A)1.2 volts    
(B)  0.4 volts    
(C) 5 volts    
(D)  0 volts
Ans: D
Explanation: CMOS logic low level is 0 volts approx.

8. Karnaugh map is used for the purpose of
(A)Reducing the electronic circuits used.
(B) To map the given Boolean logic function.
(C)To minimize the terms in a Boolean expression.
(D)To maximize the terms of a given a Boolean expression.
Ans: C

9. A full adder logic circuit will have
(A)Two inputs and one output.  
(B)Three inputs and three outputs.
(C) Two inputs and two outputs.  
(D) Three inputs and two outputs.
Ans: D Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.

10. An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately
(A)1 MHz.   
(B)  500 MHz    
(C) 2 MHz.   
(D)  4 MHz.
Ans: A
Explanation: Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.