COMPUTER SYSTEM ARCHITECTURE MCQS PART 28

COMPUTER SYSTEM ARCHITECTURE MCQS PART 28

1. As the instruction length increases ________of instruction addresses in all the instruction is_______:
a. Implicit inclusion       
b. Implicit and disadvantageous
c. Explicit and disadvantageous       
d. Explicit and disadvantageous
Answer C

2. ______is the sequence of operations performed by CPU in processing an instruction:
a. Execute cycle 
b. Fetch cycle   
c. Decode   
d. Instruction cycle
Answer D

3. The time required to complete one instruction is called:
a. Fetch time
b. Execution time
c. Control time
d. All of these
Answer B

4. _____is the step during which a new instruction is read from the memory:
a. Decode 
b. Fetch 
c. Execute 
d. None of these
Answer  B

5. ________is the step during which the operations specified by the instruction are executed:
a. Execute
b. Decode
c. Both a& b
d. None of these
Answer A

6. Decode is the step during which instruction is______:
a. Initialized         
b. Incremented         
c. Decoded          
d. Both b & c
Answer C

7. The instruction fetch operation is initiated by loading the contents of program counter into the______ and sends_____ request to memory:
a. Memory register and read           
b. Memory register and write
c. Data register and read                 
d. Address register and read
Answer D

8. The contents of the program counter is the_______ of the instruction to be run:
a. Data       
b. Address        
c. Counter            
d. None of these
Answer  B

9. The instruction read from memory is then placed in the_______ and contents of program counter is______ so that it contains the address of_______ instruction in the program:
a. Program counter, incremented and next
b. Instruction register, incremented and previous
c. Instruction register, incremented and next
d. Address register, decremented and next
Answer C
10. Execution of instruction specified by instruction to perform:
a. Operation  
b. Operands  
c. Both a & b   
d. None of these
Answer A