COMPUTER SYSTEM ARCHITECTURE MCQS PART 85

COMPUTER SYSTEM ARCHITECTURE MCQS PART 85

1. If CPU and I/O interface share a common bus than transfer of data b/w 2 units is said to be:
a. Synchronous 
b. Asynchronous
c. Clock dependent
d. Decoder independent
ANSWER A
2. All the operations in a digital system are synchronized by a clock that is generated by:
a. Clock        
b. Pulse       
c. Pulse generator        
d. Bus
ANSWER C

3. Asynchronous means:
a. Not in step with the elapse of address
b. Not in step with the elapse of control
c. Not in step with the elapse of data  
d. Not in step with the elapse of time
ANSWER D

4. ________is a single control line that informs destination unit that a valid is available on the bus:
a. Strobe          
b. Handshaking        
c. Synchronous      
d. Asynchronous
ANSWER A

5. What is disadvantage of strobe scheme:
a. No surety that destination received data before source removes it
b. Destination unit transfer without knowing whether source placed data on data bus          
c. Can’t said     
d. Both a & b
ANSWER D

6. In_______ technique has 1 or more control signal for acknowledgement that is used for intimation:
a. Handshaking         
b. Strobe
c. Both a & b    
d. None of these
ANSWER A
7. The keyboard has a__________ asynchronous transfer mode:
a. Parallel         
b. Serial       
c. Optimum       
d. None
ANSWER B

8. In _______transfer each bit is sent one after the another in a sequence of event and requires just one line:
a. Serial         
b. Parallel        
c. Both a & b      
d. None of these
ANSWER A

9. Modes of transfer b/w computer and I/O device are:
a. Programmed I/O          
b. Interrupt-initiated I/O
c. DMA    
d. Dedicated processor such as IOP and DCP
e. All of these
ANSWER E

10. ______operations are the results of I/O operations that are written in the computer program:
a. Programmed I/O
b. DMA   
c. Handshaking   
d. Strobe
ANSWER A