COMPUTER SYSTEM ARCHITECTURE MCQS PART 25

COMPUTER SYSTEM ARCHITECTURE MCQS PART 25

1. A three state gate defined as:
a. Analog cicuit   
b. Analog fundamentals  
c. Both a&b 
d. Digital circuit
Answer  D

2. In 3 state gate two states act as signals equal to:
a. Logic 0        
b. Logic 1          
c. None of these      
d. Both a & b
Answer D

3. In 3 state gate third position termed as high
impedance state which acts as:
a. Open circuit
b. Close circuit
c. None of these
d. All of above
Answer A

4. In every transfer, selection of register by bus is decided by:
a. Control signal
b. No signal
c. All signal
d. All of above
Answer A

5. Every bit of register has:
a. 2 common line
b. 3 common line
c. 1 common line
d. none of these
Answer C
6. DDR2 stands for:
a. Double data rate 2               
b. Data double rate 2
c. Dynamic data rate 2               
d. Dynamic double rate 2
Answer  A
7. SDRAM stands for:
a. System dynamic random access memory
b. Synchronous dynamic random access memory
c. Both
d. None
Answer C

8. Which is referred as a sequential circuit which
contains the number of register as per the protocol:
a. RTL        
b. RAM           
c. MAR          
d. All of these
Answer B

9. Which operation refer bitwise manipulation of
contents of register:
a. Logical micro operation          
b. Arithmetic micro operation
c. Shift micro operation             
d. None of these
Answer  A

10. Which symbol will be used to denote an micro
operation:
a. (^)          
b. (v)              
c. Both              
d. None
Answer  B