COMPUTER SYSTEM ARCHITECTURE MCQS PART 90

COMPUTER SYSTEM ARCHITECTURE MCQS PART 90

1. Intercrosses arbitration system for multiprocessor shares a _________:
a. Primary bus     
b. Common bus     
c. Domain bus    
d. All of these
ANSWER B

2. Which is used to decentralize the decision to avail greater flexibility to the system that makes processor or microprocessor in a very short:
a. Arbitration        
b. Centralized     
c. Both a & b     
d. None of these
ANSWER A

3. Which is signal tells that an arbitration of the access bus is possible during interprocessing:
a. DBA        
b. BAP         
c. BNA        
d. None of these
ANSWER B

4. Which signal bus request :
a. BAP        
b. BNA         
c. BAL            
d. DBA
ANSWER D

5. Which signal on the bus indicates that request from process arbitration is to be processed:
a. BAL           
b. BREQ         
c. BM4                 
d. DBA
ANSWER B
6. Which signal is exchange information by bus:
a. BECH          
b. BM4         
c. BAL           
d. All of these
ANSWER A

7. Which signal on bus applies +1 to the priority of resolution circuits of the arbitration designate a new arbitration:
a. BM4                
b. BAL              
c. BNA                  
d. DBA
ANSWER C

8. Which signal create 3 lines of bus in  which signals from the encoded number of processors:
a. BM1 to BM3      
b. BAL      
c. Both         
d. None of these
ANSWER C

9. Which signal request the validation signal make active if its logic level is 0 and validate signals from BM1 to BM3:
a. BAL       
b. BM4      
c. BNA       
d. All of these
ANSWER B

10. Which signal represents synchronization signal decided by interprocess arbitration with a certain delay or signal DMA:
a. BAL             
b. BNA          
c. Both           
d. None of these
ANSWER A