COMPUTER SYSTEM ARCHITECTURE MCQS PART 91

COMPUTER SYSTEM ARCHITECTURE MCQS PART 91

1. In which condition only one process holds a resource at a given time:
a. Mutual exclusion   
b. Hold and wait      
c. Both      
d. None of these
ANSWER A

2. In which condition one process holds the allocated resources and other waits for it:
a. No preemption      
b. Hold and wait       
c. Mutual exclusion
d. All of these
ANSWER B

3. In which condition resource is not removed from a process holding:
a. Synchronization problem       
b. No preemption
c. Hold and wait                          
d. None of these
ANSWER B

4. In which condition busy waiting, programmer error, deadlock or circular wait occurs in interprocessing:
a. Synchronization problem            
b. No preemption
c. Hold and wait                               
d. None of these
ANSWER A

5. Mechanism can be referred to as adding a new facility to the system hence known as _______:
a. Process      
b. Arbitration        
c. Both a & b         
d. None of these
ANSWER B

6. Which is a mechanism used by the OS to ensure a systematic sharing of resources amongst   concurrent resources:
a. Process synchronous       
b. Process system      
c. Process synchronization
d. All of these
ANSWER C
7. _________ is basically sequence of instructions with a clear indication of beginning and end for updating shared variables
a. Critical section
b. Entry section
c. Remainder section
d. All of these
ANSWER A

8. Which provides a direct hardware support to mutual exclusion
a. Test-and-set(TS)           
b. Swap instruction
c. Wait instruction            
d. Signal instruction
ANSWER A

9. A process waiting to enter its critical section may have to wait for unduly_______:
a. Short time or may have to wait forever
b. Long time or may have to wait forever
c. Short time or may have to wait for long time
d. Long time or may have to wait for short time
ANSWER B

10. Which is a modified version of the TS instruction which is designed to remove busywaiting:
a. Swap instruction
b. Wait instruction
c. Signal instruction
d. Both b & c
ANSWER D