COMPUTER SYSTEM ARCHITECTURE MCQS PART 58
1. Which control is used during starting of instruction cycle:
a. Write
b. Read
c. R/W
d. None of these
ANSWER B
2. ________function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU:
a. ALU
b. CPU
c.Memory
d. Cache
ANSWER A
3. ________is dependent on instruction type in CU:
a. Jump
b. Branch
c. NextPC
d. All of these
ANSWER D
4. __________dependent on instruction and major state and also comes in starting of data fetch state as well as write back stage in CU:
a. Register read
b. Register write
c. Register R/W
d. All of these
ANSWER C
5. _______dependence over op-code in C:
a. Load register
b. Load Reg/Reg
c. Only Load
d. None of these
ANSWER B
6. Full form of PLA in CU:
a. Progrmmable Logic Array
b. Programs Load Array
c. Programmable Logic Accumulator
d. all of these
ANSWER A
7. Which are tasks for execution of CU or MCU:
a. Microinstruction execution
b. Microinstruction sequencing
c. Both a & b
d. None of these
ANSWER C
8. Branching is implemented by depending on output of:
a. CD
b. RG
c. CC
d. CR
ANSWER A
9. Wo determine under what conditions the branhing will occur and when:
a. By cobination of CD and BT
b. By cmbination of CD and BR
c. By cobination of CD and CR
d. By combination of TD and BR
ANSWER B
10. The character U is used to indicate:
a. Undefined transfers
b. Unfair transfers
c. Unconditional transfers
d. All of these
ANSWER C
a. Write
b. Read
c. R/W
d. None of these
ANSWER B
2. ________function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU:
a. ALU
b. CPU
c.Memory
d. Cache
ANSWER A
3. ________is dependent on instruction type in CU:
a. Jump
b. Branch
c. NextPC
d. All of these
ANSWER D
4. __________dependent on instruction and major state and also comes in starting of data fetch state as well as write back stage in CU:
a. Register read
b. Register write
c. Register R/W
d. All of these
ANSWER C
5. _______dependence over op-code in C:
a. Load register
b. Load Reg/Reg
c. Only Load
d. None of these
ANSWER B
6. Full form of PLA in CU:
a. Progrmmable Logic Array
b. Programs Load Array
c. Programmable Logic Accumulator
d. all of these
ANSWER A
7. Which are tasks for execution of CU or MCU:
a. Microinstruction execution
b. Microinstruction sequencing
c. Both a & b
d. None of these
ANSWER C
8. Branching is implemented by depending on output of:
a. CD
b. RG
c. CC
d. CR
ANSWER A
9. Wo determine under what conditions the branhing will occur and when:
a. By cobination of CD and BT
b. By cmbination of CD and BR
c. By cobination of CD and CR
d. By combination of TD and BR
ANSWER B
10. The character U is used to indicate:
a. Undefined transfers
b. Unfair transfers
c. Unconditional transfers
d. All of these
ANSWER C
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