COMPUTER SYSTEM ARCHITECTURE MCQS PART 57

COMPUTER SYSTEM ARCHITECTURE MCQS PART 57

1. Full form of FSM is:
a. Finite state machine
b. Fix state machine
c. Fun source metal
d. All of these
ANSWER A

2. Rules of FSM are encoded in:
a. ROM
b. Random logic
c. Programmable logic array 
d. All of these
ANSWER D

3. In RISC architecture access to registers is made as a block and register file in a particular register can be selected by using:
a. Multiplexer   
b. Decoder   
c. Subtractor      
d. Adder
ANSWER B

4. Outputs of instruction/data path in CU are:
a. Reg R/W  
b. Load/Reg-Reg  
c. ALU function select 
d. Load control
e. Read control  
f. IR Latch  
g. JUMP/Branch/Next PC 
h. All of these
ANSWER H

5. One last bit of control output is for control of_______ state:
a. Minor 
b. Major   
c. Mixer    
d. None of these
ANSWER B

6. Following are 4 major states for ‘load’ are:
a. Fetch       
b. Decode        
c. Memory
d. Write back 
e. All of these
ANSWER E

7. Jump has 3 major states are:
a. Fetch     
b.Decode    
c.Complete   
d.All of these
ANSWER D

8. ________ state keeps track of position related to execution of an instruction:
a. Major      
b. Minor       
c. Both a & b  
d. None of these
ANSWER A
9. An instruction always starts with state___:
a. 1    
b. 2      
c. 3       
d. 0
ANSWER D

10. Decoding of an instruction in RISC architecture means decision on working of control unit for:
a. Remainder of instructions
b. Divisor of instructions
c. Dividend of instructions 
d. None
ANSWER A