COMPUTER SYSTEM ARCHITECTURE MCQS PART 33

COMPUTER SYSTEM ARCHITECTURE MCQS PART 33

1. It contains the ____________stack for PC storage during subroutine calls and
input/output interrupt services:
a. Seven- level hardware     
b. Eight- level hardware
c. One- level hardware        
d. Three- level hardware
Answer B


2. Which unit works as an interface between the processor and all the memories on chip or off- chip:
a. Timing unit
b. Control unit
c. Memory control unit
d. All of these
Answer C

3. The maximum clock frequency is_______:
a. 45 MHZ   
b. 50 MHZ  
c. 52 MHZ       
d. 68 MHZ
Answer B

4. ________ is given an instruction in machine language this instruction is fetched from the memory by the CPU to execute:
a. ALU       
b. CPU       
c. MU       
d. All of these
Answer B
5. Which cycle refers to the time period during which one instruction is fetched and executed by the CPU:
a. Fetch cycle    
b. Instruction cycle  
c. Decode cycle  
d. Execute cycle
Answer B

6. How many stages of instruction cycle:
a. 5        
b. 6        
c. 4          
d. 7
Answer C

7. Which are stages of instruction cycle:
a. Fetch   
b. Decode      
c. Execute
d. Derive effective address of the instruction  
e. All of these
Answer E

8. Which instruction are 32 bits long , with extra16 bits:
a. Memory reference instruction   
b. Memory reference format
c. Both        
d. None of these
Answer A
9. Which is addressed by sign extending the 16-bit displacement to 32-bit:
a. Memory address     
b. Effective memory address
c. Both a and b      
d. None of these
Answer B

10. Which are instruction in which two machine cycle are required:
a. Instruction cycle
b. Memory reference instruction 
c. Both
d. None of these
Answer B